Electronic sorting system



April 6, 1954 H. M. RoBBlNs v 2,674,733

ELECTRONIC SORTING SYSTEM Filed Dec. 2, 1952 2 Sheets-Sheet l E K INVENTOR. A/a/v// /z [jaaa/,w l .2.7222- Z, BY

H. M. ROBBINS ELECTRONIC SORTING SYSTEM April 6, 1954 2 Sheets-Sheet 2 Filed Dec. 2, 1952 Irfan; Y.

Patented Apr. 6, 1954 ELECTRONIC SORTING SYSTEM Howard M. Robbins, Los Angeles, Calif., assignor to Hughes Tool Company, Houston, Tex., a corporation of Delaware Application December 2, 1952, Serial No. 323,624

1a claims. l

This invention relates to electronic sorting systems, and more particularly to high-speed electronic sorting systems for re-recording randomlyrecorded information groups in a predetermined, evenly-spaced sequence.

Although numerous types of sorting systems are known in the art, these systems may be divided into two generalclasses according to the type of sorting program utilized. In systems of one class, hereinafter referred to as parallel sorting systems, each successive information group is selectively routed to one of a plurality of positions, according to a predetermined sorting function. The punched card sorting system, for example, is a parallel sorting system wherein the selected positions are bins"; the cards being entered therein according to certain punched identification codes.

Another example of a parallel sorting system is one wherein randomly-recorded magnetic information on an input tape is selectively transferred to one of ten tapes according to a decimal identification character included in each information group. Other examples of parallel sorting systems are described in an article entitled Sorting and collating, by John W. Mauchly, in vol. III of Theory and Techniques for Design of Electronic Digital Computers, Moore School of Electrical Engineering, University of Pennsylvania, June 30, 1948, on pages 22-25.

Sorting systems of the other class are herein referred to as serial sorting systems, and are distinguished from the parallel systems in that only certain ones of successively appearing information groups are selected; the sorting being performed by passing the information groups through `the sorting system a number of times until all of the information groups are arranged into the desired sequence. Thus, in a serial sorting system for transferring randomly-recorded magnetic information from an input tape onto an output tape, in sequence according to decimal identification characters, the input tape must be passed through the system several times before the information groups are all recorded on the I output tape according to one decimal digit.

In general, prior art parallel sorting systems have been preferred over serial sorting systems since the former systems readily lend themselves to high-speed operation and present no problem in obtaining a nal, evenly-spaced record according to a predetermined sequence.

The high-speed operation of the parallel system is primarily due to the fact that the information to be sorted need only be scanned or passed as many times as there are code characters in the identification code nember of each information group. For example, information concerning corporate employees, having flve-decimal-digit payroll numbers, may be sorted in five passes. Thus, punched cards are passed through the sorting system into the ten bins only five times in order to get all cards in order according to a live-decimal-digit number; the final sequence being obtained by integrating the information in the bins" into serial order.

In the serial sorting systems, a number of subsequences are required to arrange the information groups into nal sequences according to a code character. Thus, while the parallel system requires only one pass to arrange employee information into bins according to one decimal digit, the serial sorting system requires several passes depending upon the particular code utilized. If each decimal digit of the code number is binary coded, at least seven passes are required before a first sequence is formed wherein information groups are arranged in serial order according to the least significant decimal digit. Thus, at least seven times as many passes are required to completely sort information groups containing binary-coded decimal code identification characters in serial fashion as are required to sort the same information in the parallel manner.

Another disadvantage of serial sorting systems is that where tape-recorded information is utilized, it is difficult to integrate the sorted information into an evenly-spaced record which may be recorded on an output tape. As each sequence is formed, the selected information groups appear in a randomly-spaced sequence since only certain groups are read from the input tape according to the sorting program. Consequently, if several sub-sequences are required to form a sequence, a considerable amount of tape is required to allow for the spaces between the selected groups.

Serial sorting systems, however, have a decided advantage over parallel systems with respect to system complexity In the serial systems, the same structure may be utilized to perform successive steps of the sorting process, Whereas in the parallel system, the structure must `be duplicated according to the number of positions required. Thus, in the simple case of card sorting,

overcome the principal disadvantages of the serial sorting systems discussed above, they have not realized the advantage of simplicity. The present invention, however, discloses a novel, serial sorting system which obviates the above and other disadvantages of the prior serial sorting systems, may be operated a-t high speed, and does not require additional tape storage capacity.

According to the basic concept of the present invention, randomly-recorded input information is passed through a selecting device which produces a randomly-spaced sequence corresponding to the selected information groups. The randomly-spaced sequence is then converted to corresponding evenly-spaced sequence by means of a novel variable delay circuit. The variable delay circuit responds to sets of output signals corresponding to the selected, randomly-spaced information groups and produces corresponding evenly-spaced sets of output signals. This is done under the control of a delay control circuit which responds to signals produced by the selecting device, indicating spaces in the selected information, and varies the delay of the delay circuit according to a predetermined function.

Since the variable delay circuit has a multitude of applications, only a brief description thereof is included in the present application, reference for further details being made to copending U. S. patent application entitled Variable Delay Means, by Howard M. Rob-bins, Serial No. 323,623, led December 2, 1952.

The high-speed embodiments of 'the present invention are provided by using a magnetic drum to perform the function of passing the randomlyrecorded information under reading heads. Since the magnetic drum may be operated at speeds ranging from ten to twenty times the maximum operating speed permissible with magnetic tape, it is possible to perform serial sorting operations as fast, if not faster, than corresponding parallel sorting operations on magnetic tape.

Accordingly, it is an object of the present invention to provide a serial sorting system requiring a minimum of storage capacity,

Another object of the present invention is to provide a high-speed serial sorter.

A further object of the present invention is to provide a simple, high-speed serial sorter system requiring a minimum of storage capacity.

Yet a further object of the present invention is to provide a high-speed magnetic drum sorting system.

Still another object of the present invention is to provide a novel system for selectively sorting randomly-recorded information groups and recording said groups into a predetermined, evenly-spaced sequence. v

The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages thereof, will be better understood from the following description considered in connection with the accompanying drawings, in which several embodiments of the invention are illustrated by Way of examples. It is to be expressly understood, however, thatthe drawings are for the purpose of illustration and description only, and are not intended as a 'definition of t'he limits of the invention.

Fig. l is a block diagram of an embodiment of the present invention;

Figs. 2a and 2b are schematic diagrams of suitable forms of the selecting means shownin Fig. l;

Fig. 3 is a schematic diagram of one form of the gating means shown in Fig. 1;

Fig. 4 is a schematic diagram of one of the circuits forming the sequence control means shown in Fig. 1;

Fig. 5 is a schematic diagram of one form of the variable delay means shown in Fig. 1; and

Fig. 6 shows a magnetic drum and associated circuits utilized in high-speed sorting systems according to the present invention.

Referring now to Fig. l, there is shown one embodiment of a serial sorting system according to the present invention in which serially-applied, randomly-recorded information groups are sorted and recorded in a predetermined, evenlyspaced sequence. As shown in Fig. 1, the sorting system comprises: selecting means |00, responsive to information signal groups produced by a signal source 200, for producing complementary electrical binary control signals Bc and Bc corresponding to each information signal group to control its selection or nonselection; gating means 300, responsive to signals Bc and to the information groups applied after a fixed delayv for producing randomly-spaced sets of output signals Oi, corresponding to the selected signal groups; a delay circuit 400 providingv the xed delay; and variable delay means 500 responsive to randomly-spaced signal sets O1 for producing evenly-spaced signal sets O2.

The delay of signal groups O1 through variable `delay means 500 is controlled by signals De produced by delay control means 600 in response to signals Bc; and the operation of selecting means |00 and gating means 300 is controlled by signals produced by sequence control means 100.

The structure of selecting means |00, gating means 300, varia-ble delay means 500, and delay control means 600 is determined by the particular code which is utilized to identify the information groups, as Well as the sorting program which is adopted. Therefore, before proceeding to con- Sider the details of these structures, it is necessary to consider various codes and sorting programs.

As an illustrative problem, consider the sorting of randomly-recorded information groups containing binary-coded decimal identification numbers, Where it is desired to arrange the groups into a sequence wherein the identification codey numbers of all groups are in serial number order. It is assumed that the least significant binarycoded decimal digits of the respective identification numbers appear in the following random sequence:

Leut Sig- Sequence Position njllcant Decimal Digit Thus, the least signi-- iicant deci-mal digits appear in the following order in the first sub-sequence:

1st subway uence First pass-al1 first binary 1000 digits are s Second pass-all nrst binary digits are ls The first sub-sequence is then read and recorded as a second sub-sequence after third and fourth passes by recording information groups having 0s and 1s, respectively, in the second binary place of the least significant binary-coded decimal digit. The decimal digits in the second sub-sequence then appear in the following order:

2nd rub-sequence 0100 4) 1000 8) 0000 0g Third pass-al1 second binary 0101 (5 digits are 0s 0001 (1) 1001 (9) 0010 (2) 0110 (6) Fourth pass-all second binary 0011 (3) digits are l's 0111 (7) Sorting according to the first decimal digit is then completed by forming third and fourth subsequences according to the third and fourth binary digits, respectively. During the first pass of each of these sub-sequences, information groups containing 0s in the corresponding binary place are recorded, and during the second pass of each of these sub-sequences, those information groups having a 1 in the corresponding binary place are recorded. The third and fourth sub-sequences then appear as:

3rd aub-sequence l; Fifth pass-all third binary g digits are 0s (3 4th sub-sequence EJ 0010 E Sixth pass-all third binary digits are ls Seventh pass-all fourth binary digits are 0s 1000 (8 El hth pass-all fourth 1001 (9) inary digits are 1s places. Similarly, decimal digits having 00, 01,

`and 10 in the third and fourth binary places are .recorded during the first, second, and third passes of the second sub-sequence, respectively. It will be noted that after the seventh pass, the digits are in serial number order. The sub-sequences according to the seven-pass sorting program appear as follows:

1st aub-sequence 2nd aub-sequence 5 (gg First pass (00) 0.88111 (o) 0000 (o) lo Fifth pass (oo) 0101 (5) 0001 (1) Secondpass (01) 0100 (4) 1001 (9) 0101 (5) 10 0110 s) sixth pass (o1) glg 'rim-d pass (1o) 0111 (7) 1000 8 Seventhpass (10) 32g rourchpss (u) 1001 93 In the above analysis, sorting according to one binary-coded decimal digit has been considered. It should be apparent. however, that the process must be repeated for each of the binary-coded decimal digits in a multidigit identification code number. Where binary-coded information is sorted by considering one binary digit at a time, then the number of passes required is equal to 2.11..N, Where 11. represents the number of binary digits in each character and N represents the number of characters in the identification code. Where the sorting is performed by considering two binary digits during each pass, the total number of passes required is less than 2.n.N by a factor which depends upon the code which is utilized. It has been shown that only seven passes are required for sorting the binary-coded decimal digits, as above, and thus the total number of passes required for N digits is 7 N. Similarly, it

can be shown that alphabetical information containing binary-coded letters may be sorted in 9.N passes, although each letter is represented by six binary digits.

Binary-coded decimal numbers may be sorted by considering three or four binary digits at a time. However, this sorting program would require ten passes for each decimal digit or a total of 10.N passes. The advantage, however, of sorting by all four binary digits is that only one subsequence is required, and, therefore, it is not necessary to transfer from one record to another as frequently as would otherwise be necessary.

,The reason for this is explained more fully below.

While embodiments of the present invention may be utilized to sort information groups identied by other code characters, such as characters in the IBM Hollerith code, binary codes are preferred where it is desired to minimize the storage capacity and the number of passes required.

The discussion which follows concerns sorting structures specifically designed for systems wherein the identification characters are binary coded. It should be understood, however, that the present invention is not so limited and that the principles hereinafter set forth are applicable to a wide variety of codes.

Programs for sorting binary-coded information may be expressed as Boolean algebraic functions, Where binary variables are utilized to express the particular pass, the particular identification character, and the particular binary digit which is to be analyzed. Hereinafter, each pass is designated by a binary variable PU), where j indicates the number of the pass. The variable PU) has a value of 1 when the particular pass is to be performed; otherwise its value is 0. Similarly, the binary digits in the identification code characters are represented by variables Bdk, where 7c indicates the binary place. Thus, Bdl represents a first binary digit in a code charwana acter, k. being equal to 1. the particular character which is .to be analyzed is represented by Cam, where m represents the position of the character in the identification code number; C41, for example, representing the` first character in the indenticaton code number, where 1h is equal to 1. Corresponding to each of the binary digit variables Bd", there is a complementary variable Eik having values of land 0, respectively, when Bdc equals and l, respectively.

With these variables, then it is possible to dene a binary control signall B and a complementary binary control signal Bc having values of 1 and 0 when a particular group is to be selected or recorded into a sub-sequence, and having values of 0 to 1 when a group is not to be selected.

It will be recalled that in sorting by one binary digit at a time, information groups are recorded in a first sub-sequence by recordingk groups including a 0 first binary digit, during the first pass, and then recording groups including a 1 first binary digit, during the second pass. Thus, the binary control signal Bc has a value of 1 for all identication code characters if the first binary digit is 0 on the first pass or if the first binary digit is 1 on the second pass. Algebraically, this is expressed as follows:

Where the dot expresses the logical and and the plus sign the logical on This expression is interpreted as follows. has a value of 1, indicating that an information group is to be recorded into a sub-sequence, whenever the mth identication character is being read, as indicated by Vari-able Ca,m being equal to 1; and either P(1) and Bdl are equal to 1 or P(2) and Bd1 are equal to 1, indicating a 0 in the first binary digit on the first pass, or a 1 in the first binary digit on the second pass, respectively. This analysis is then completed for all passes and binary digits, the complete function for Bc then becoming:

Where the sorting is performed by considering r where it is assumed that each code character is a binary-coded decimal digit.

Where the sorting is performed by considering one binary digit at a time, a new sub-sequence is formed for every two passes. Thus, the second binary digit is read from a different record than the first. Where erasable magnetic recording is utilized, it is possible to alternate between first and. semmaiA sets of recording channels so that The variable Bc after each two passes, the signals read from' the same magnetic storage channels. If pimched tape is utilized, however, it is apparent that a new tape is required for recording each sub-sequence, For the purpose of illustrating specific structure, it is assumed hereinafter that two sets of magnetic drum channels are used.

The input signals produced by the first and second sets of channels of the magnetic drum are hereinafter referred to as Iak and Ibk, respectively; where k corresponds to the binary digit which is represented. Circuits fir; deriving com" plementary input signals Iak, Iak and Ibk, IbIc from drum signals Iak and Ibk are well-known in the art. For example, the magnetic disk reading circuits shown in U. Si. Patent No. 2,609,143, entitled Electronic Computer for Addition and Subtraction, by G. R.. Stibitz, issued September 2, 1952, are suitable for providing the complementary signals.

In considering the actual circuit mechanization then, signals Ia'c and Ia7c are substituted for the variables Bdk and Bd.k whenever k is an odd number; and signals Ibk and Ibk are substituted for the variables Bdc and Bdk whenever k is an even number. Thus, the algebraic expression for binary control signal Bc for sorting according to one binary digit at a time becomes:

Where it is assumed that n is an even number.

It will be recalled that when the two binary digits are considered at a time, the same variables Bdk and Bd7c are considered for four passes in succession. Thus, it Will be noted in the function for Bc, where two binary digits are considered at a time, that signals Ia'c and llac are utilized for four successive passes and then signals Ibc and IbIc are utilized for four successive passes. The function Bc, considering two binary digits at a time, then is:

where it is assumed that 11, equals 4 and that binary-coded decimal digits are to be sorted.

Before proceeding to consider: the details of the mechanizations suitable for selecting means I 00 (Fig. l), it is important to consider the sequence of the sorting operation. Since the information which is to be sorted, must be selected before passing through gating means 300, it is necessary that it be. delayed so that signals Bc and Bc, corresponding to the desired selection, are produced just before the corresponding information group is applied through delay circuit 400 to gating means 300. For the present, it is assumed that the delay provided by delay circuit 400 is equal to the length, in time, of an information group, although it will be shown that other delays may be suitable.

Since it has been assumed that delay circuit 400 provides a delay equal to the length of the information groups, each signal Bc must not become effective to actuate gating means 30|)y until the end of the corresponding group. lIhis operation may be effected by first entering, signal Bc, as produced, into a first flip-flop, andy then shifting signal Bc intoa second flip-flop at the end of the corresponding information group or at the beginning of the next group.

In selecting means Hill, themrst and second flip-flops, FI and F2, are utilized to provide the operation described above. Flipflops FI and F2 have I and 0 setting input circuits referred to, respectively, as IFI, FI and IF2, 0F2 and produce complementary output signals F1, F1 and F2, F, respectively. When signals are applied separately to the I and 0 circuits of a flipflop, it is set, respectively, to stable states representative of binary 1 and 0; when signals are applied to both input circuits of a flip-ilop, it is triggered or complemented.

In order to enter signals Bc into flip-nop FI, it is necessary to provide pulse entry signals which will set the flip-nop to the desired stable states. 'Iliis may be provided by recording a clock pulse signal, herein referred to as signal Cp, adjacent to each character position on the drum. Thus, when the mth code character Cam is being read and signal Bc is equal to l, a clock pulse signal from the drum sets flip-flop FI to 1. On the other hand, if Bc is equal to 0, the clock pulse Cp does not pass to the ip-op and it will remain set to 0.

At the end of each group, then, signal Bc, stored in ip-op FI, is shifted into flip-flop F2 by means of one of group pulse entry signals Gp, recorded on the magnetic drum, one at the end of each infomation group. Signal Gp is also utilized to set ip-op FI to 0 at the end of the group so that it is prepared for the entry of the next signal Bc, indicating the selection or nonselection of the next information group.

It will be noted, then, that flip-flop signals F2 and produ ced by nip-flop F2 correspond to signals Bc and Bc produced during the preceding information group.

The input circuits for flip-flops FI and F2 may be expressed as Boolean algebraic equations, as follows:

'I'hese functions are interpreted as follows. Flip-op FI is set to 1 whenever Bc is 1 and a clock pulse Cp is applied to input circuit IFI; and is set to 0 by signal Gp applied to input circuit 0FI Each time flip-flop FI is set to 0 by signal Gp, signals F1 and F1 produced by flipd op FI and corresponding, respectively, tg Bc and Bc, are shifted into ilip-op F2, signal F1 to input circuit 0F2 and signal F1 to input circuit IF2.

Two mechanizations of control means |00 are illustrated in Figs. 2a and 2b Where the functions for Bc, considering one binary digit at a time and two binary digits at a time, are mechanized, respectively. Since the manner in which these circuits are mechanized should be apparent from one example, only the circuit shown in Fig. 2a is considered in detail.

Referring now to Fig. 2a, it will be noted that the control means therein illustrated comprises two flip-flops FI and F2 and logical matrices I I 0 and I20 mechanized to provide input signals for iiip-ops FI and F2, respectively. The equations which are utilized to mechanize logical matrices IIO and |20, shown below, are given equation numbers (110) and (120), respectively.

being applied In mechanizing a logical matrix, according to a mechanization function, each and function is provided by an "and circuit which produces an output signal having a level representing binary 1 only when all applied input signals have a level representing binary 1, and each or function, indicated by a plus sign is provided by an or circuit which produces an output signal having a level representing binary 1 when any one. or more, of the applied input signals have a level representing binary 1. Thus, the and function Ca"1.[P(l).I-a1 P(2n).Ib"l.Cp is provided by and circuit II2 having signals Cam.[P(1).Ia1 P(2n).lb], and Cp applied to separate input terminals; and function P(1) .Ia1 is provided by and cir-cuit H4 having signals P(1) and .1711 applied to separate input terminals; and or function is prolided by an or circuit I I6 having signals P(l).Ia1, and P(21z).1bn applied to separate circuits are shown on pages 37 to 45 of High- Speed Computing Devices by Engineering Research Associates, pulblished in 1950 by McGraw- Hill Company, Inc., New York and London, and

. in an article entitled Diode coincidence and mixing circuits in digital computers, by Tung Chang Chen, in vol. 38 of the Proceedings of the l Institute of Radio Engineers, May 1950, on pages 511 through 514.

In one form delay means 400 may comprise two sets of magnetic reading heads spaced apart being applied on the magnetic drum a distance equal to the length of one information group, plus any space between groups. Selecting means |00 is then r made responsive to signals produced by one of the sets of reading heads and gating means 300 f is made responsive to signals produced by the other set, such that signals corresponding to an information group are applied first tol selectj ing means |00 and then, after a one group-timeplus-space delay, to gating means 300.

Other types of delay devices, however, may be utilized. For example, suitable delay devices are shown in an article entitled Mercury delay line memory using pulse rate of several megacycles,

by I. L. Auerback, in vol. 3'7 of Institute of Radio Engineers Proceedings, August 1949, on pages 855-861; or in U. S. patent application, Serial No. 300,28,6, entitled Passive Element Signal Stepping Device, by Daniel L. Curtis, filed July 22, 1952.

In sorting according to one binary digit at a time it will be noted that selecting means |00 responds to signals Ia'c during passes P(l), P(2) 11 P(2n-3), and P(2n-2); and responds to signals Ibk during passes P(3) P01) P(2n-1) and P(211.). It is convenient, therefore, to introduce the variables P's and Ps having values representing binary 1 during the reading of signais Ia.k and Ibk, respectively. 'I'hus variable Ps=P(1)+P(2)+ P(2n-3)+P(2n2) and variables Ps- -P(3) -l-Pii) P 2n-l +P(2n). Variables Ps and Ps are complements because there are 2n pass-indicating variables, and the indication that one oi' a set of n passes is being performed must mean none of the other set of n passes is being performed. The manner in which corresponding signals Ps and Ps are produced by sequence-controlling means '|00 is explained in detail below.

It will be recalled that gating means 300 produces sets of signal O1 corresponding to the selected sets of input signals. It should be apparent, then, that when signal Bc is equal to 1, signals O1 correspond to signals Ick, if Ps equals 1, and correspond to signals Ibk, if Pls equals l. Thus, the mechanization of gating means 30G may be defined by the Boolean algebraic expression variables Ps and Ps may be defined as follows:

here the total number of passes is limited It can be seen, therefore, that' gating means 3M not only functions to produce signals corresponding to selected information groups, but also responds to signals Ps and Ps and selects between the iirst and second sets of drum channels according to the function inherent in signals Ps and 15s.

A mechanization suitable for gating means 300 is shown in Fig. 3 The manner in which the functions are mechanized should be apparent from the examples already given.

When a magnetic drum is used in the sorting system, each pass is equivalent to one drum revolution. It is possible, then, to count the number of passes by counting the drum revolutions. The pass, indicating signals P(1), P(2), P(2n), may then be produced by a counter which is pulsed once for each drum revolution, the pulse being provided by a signal which is recorded on the drum, such as signal Gp.

The counter which is utilized must complete one counting cycle for each sorting sequence. Thus, where 12 passes are required to form each sequence, a 12-stable-state counter is utilized.

While any of the conventional counters may be utilized, it is convenient to use a binary counter having as many stages as are necessary to provide the desired number of stable states. Where the binary counter produces more stable states than required, it may be converted into the desired counter Vby means of feed-back connections wellknown in the art. The basic technique, for example, of converting 64-stable-state binary counters into a 6Dstablestate counter by means of feed-back connections, is shown and described in U. S. Patent No. 2,410,156, entitled Electronic Timing Device, by L. E. Flory, issued October 29, 1946.

When a binary counter is utilized, signals Ps and P s for sorting according to one binary digit, may be derived from the second stage of the counter, since this stageproduces signals which are on and off alternately, every two counts. Similarly, signals Ps and E, for sorting according to two binary digits at a time, may be derived from the third stage of the binary counter, since this stage produces signals which are alternately on and off every fourth count.

In addition, to producting pass-indicating signals, sequence control means |00 produces signals Caf" corresponding to the particular character which is to be utilized. A circuit suitable for producing signals Caf is shown in Fig. 4. In the circuits shown in Fig. 4 signal Ca,m is produced as a function of two signals C1 and CE produced by iiip-fiops CI and C2, respectively. This function is: Cam=C1.C2. Flip-flops CI and C2 are connected in series in a circulating or shifting register having a circulation length equal to the length of the information groups to be sorted plus any space between groups. Thus, if each information group is digits in length and is spaced by one digit from the next group, the circulating register must have an 81 digit capacity.

Where a magnetic drum is utilized, a circulating register may be provided by writing the signals to be circulated on the drum at one point, reading the signals which were Written at a second point, and then re-recording these signals vat the first point. The reading and writing heads,

then, are separated on the drum by a length equal to the circulating-register length desired, less a. space corresponding to the two digits provided by iiip-flops CI and C2.

Other types of circulating registers which are suitable are shown and described in an article entitled Gate-type shifting register, by J. H. Knapton and L. D. Stevens, in vol. XXII of Electronics, December 1949, on pages 186-192, and in copending U. S. patent application entitled Passive Element vSignal Stepping Device, by Daniel L. Curtis, Ser. No. 300,286, filed July 22, 1952.

When the circulating register is not on the magnetic drum, it is Ynecessary to synchronize its operation with the application of the information groups to selecting means |90, so that the circulating register completes one cycle during the application of each information group.

At the start of the soridng operation, the circulating register is preset with a 1 in each place corresponding to an identification character and a 0 in each of the other places. The 1s are positioned so that when the iirst code character Cal is to be read during the formation of the first sequence, flip-flop CI stores a 1 and flip-flop C2 a 0. Thus, during the forming of the first sequence, the function 01.02 becomes 1 whenever the first code character Ca1 is being read.

After the first sequence is formed, the pass counter returns to its starting state, signalling that the next identification character is to'be considered or that the second sequence is to be formed. lIt is necessary, then, that the function 01.02 become 1 when the second identification character is being read. This operation is pro- 13 vided by eliminating the ilrst 1 which originally was present in the circulating register, so that signal C1 does not become 1 until code character Ca.2 is being read. The l'signals in the circulating register, then are eliminated, one at a time, in succession, at the end of each sequence.

In the circuit shown in Fig. 5 the 1 signals are eliminated under the control of signal C3 produced by a nip-flop C3. Signal C3 controls the shifting of signal C1, produced by nip-nop C I, into ip-iiop C2, so that whenever signal C3 is equal to 0, a 1 signal in flip-nop CI cannot enter into flip-flop C2.

Flip-flop C3 is set to 0 at the end of each sequence by a pass counter carry pulse Pc, signalling the end of a counter cycle. Thus, at the end of each counter cycle or each sorting sequence signal C3 becomes 0, preventing the entry of a 1 into flip-iiop C2. In order to prevent the elimination of more than one 1 from the circulating register at a time flip-flop C3 is set again to 1 in response to the function 01.02.

The Boolean algebraic expressions defining the input circuits for nip-flops C2 and C3 then are:

where signals Cp are utilized to shift signals C1 into flip-ilop C2, except when C3 is equal to C.

It will be noted that during the first pass of each sequence except the rst, two code characters are considered since the function 01.02 remains 1 during the time that the shift between ilip-ops Cl and C2 is prevented by the condition: C3=0. This causes no difficulty since it merely means that selecting means |00 makes two decisions, the latter of which determines the value of signal Bc.

In the above discussion it has been shown how selecting means |00 produces signals Bc and l'c corresponding to the desired sorting selection, how gating means 300 operates in response to signals Ia* and Ibk to produce corresponding sets of signals O1 when signal Bc is equal to 1, and that no output signals are produced when B E is equal to 1. It is now necessary to consider the manner in which variable delay means 500 responds to sets of signals O1 and delay control signals De, produced by delay control means B00, 'i

to produce evenly-spaced sets of output signals Oz It will be recalled that whenever an information group is rejected, signal c is equal to 1. s1gna1 T33, then, may be utilized to indicate the spaces between the selected groups in signal sets O1, or to control the operation of delay control means 600. At the end of each information group, then, as indicated by signal Gp, a signal is applied to delay control means Gull, if IEE is equal to 1.

The delay provided by variable delay means 500 must be decreased each time an information group is rejected. In its simplest form, then variable delay means 500 may comprise a plurality of equal delay sections, each section having a length represented by the function FX (GH-S) where F is an integer, which is considered in more detail beolw; Gl is the length of the in- 14 digitv'length of the magnetic drum, less'the delay provided by delay circuit 400.

While the equal-delay-section type of delay is simple in concept, it is very complicated in structure, since it requires a great number of delay sections plus a great many gating cirfcuits in order to bypass certain delay sections each time the delay is to be decreased. Consequently, it is preferred to use a variable delay circuit of the type claimed in the above-mentioned copending application to Robbins, Serial No. 323,623, one embodiment of which is shown in Fig. 5 of this specification.

In the variable delay circuit shown in Fig. 5, J delay sections are utilized such that is equal to one group-length-plus-space less than the circumferential-digit length of the drum.

If, for example, (GH-S) is equal to 8l digits, and

the circumferential-digit length of the drum is l 1296 digits, then J is equal to 4.

V plementary delay signals lief produced by delay control means 50|! are utilized to control the operation of by pass gating circuits SGU-, there being one bypass gating circuit for each delay section. Consequently, when a Signal Del is equal to 0` and Def is equal to 1, the :ith delay section is bypassed and signals passed directly through the ith bypass gating circuit 50B-7'.

Since each delay section is bypassed when the corresponding signal Bev' is equal to 1 and is passed through when Dej is equal to 1, it is possible to denne each of the delays which may be provided by delay means 500 as an and function of signals Dei and Eef. Thus, a delay of 15 Gl-|-S) is expressed as:

De1.De2.De3.De4

indicating that delay sections providing delays of 1, 2, 4,-and 8 (GZ-;S) are included; and a delay of 10 (GZ+S) is expressed as:

indicating that signals pass through delay sections providing delays of 2 and 8 times (GH-S) and bypass delay sections providing delays of 1 and 4 times (GZ-l-S).

The delay sections of variable delay means 500 may be of the same type described above with `regard to delay means 400. Where a magnetic drum is utilized to provide both delay means 400 and the delay sections of variable delay means Y 5GB, it may be convenient to utilize the drum as well to provide signal source 200, and the circulating register included in sequence control means 100. The manner in which reading, Writing and reading-writing magnetic heads are arranged into a system wherein signal source 200, delay means 40D, the delay sections of variable delay means 5519, andthe circulating register of `.sequence control means 'm0 are al1 provided by a magnetic drum, is show nin Fig. 6.

.Referring now to Rig. 6, it will be noted that channels 1 through 2n of drum 1680 are utilized for the reading of signals Iak and Ibk and for 'the of signals Oc". Reading-writing heads 60m are utilized to read signals Ia* and Ito write signals 02k, produced by the variable delay circuit 5M during the reading of signals Ibi; and reading-writing heads 602i) are utilized to read signals Il:k and to write signals 02k, during the reading of signals Iak. Reading heads 604 are utilised in delay means Il!!! and are spaced at a distance equal to (GH-S) digits from the corresponding reading-writing head 602. Thus, each reading head 6.04 produces output signals Iac or Ibi, corresponding to vsignals Ick or Ibc read by the reading-writing head 602, on the same channel, after a delay equal to (GH-S) digits.

The reading and writing heads in channels (2n-Hl) through 311 of drum 600 are utilized in the delay sections of variable delay means 5M. Writing heads 686 are utilized to record signals 01k and reading heads 698 to read corresponding signals 01k, after a delay of (Gl-JFS) digits, thus providing a iirst delay section for variable delay means 500. Each writing head 606 is actuated only when signal De1 is equal to l. Otherwise, as has been explained, signals are caused to bypass the delay section through a corresponding bypass gating circuit. For simplie/ity, the lreading and writing heads for the 2nd through the (J-llst delay sections are omitted, and Writing heads 64B and reading heads SI2 shown in Fig. 6 are utilized in the Jth delay section of variable means 500. Writing head SIB and reading head 612 are spaced by 2f-1 (GH-S) digits, as has been explained above.

In specifying the delays which are provided by the magnetic drum, it is assumed that any delay required in reading signals from, or recording signals on the drum is compensated for by a. physical positioning of the reading and writing heads. Thus, in providing the delay 0f discussed above, the writing head 610 and reading head E12 must be somewhat closer than digits, since a short time interval is required for reading and writing signals on the drum.

Channel (31H4) of drum Btl) is utilized in the circulating register of sequence control means 100. N magnetic spots, 620, are recorded on channel (311+ 1), corresponding to N code characters to be read. Magnetic spots 620 are read by reading head 62| and are then recorded by writing head 622, so that a drum circulation path of [IGl-1S 2l digits is provided, where two digits are eliminated to provide for the registry of ilipilops Ci and C2, as explained above.

Channel (3u-+2) is utilized to yprovide signals Cp, one for each of `the digits in the circumferential length of drum B90; channel (Bn-H3) provides group-end indicating signals Gp; and iinally, channel (3u-g4) provides start `signals St, the utilization of which is explained below. Signals Cp, Gp, a-nd St are read by reading heads, 630, Mil, and 650, respectively.

At the start of the sorting operation (which may be initiated in a manner described briey below) signals Ick read by reading head 502e, are ccmvertepii infto corresponding complementary signals akla", as explained above, and lare then applied to selecting Imeans |00. At the same .in `nip-flop Fl i6 time, that Vsignals Iac and Ick are entered into selecting means H30, the first l signal on channel (Sn-i-l) is entered into flip-flop CI, so that: Co:C1.C2:l. Selecting means 'lil then produces a signal Bc corresponding to the desired-.selection, signal Bc vbeing entered into flip-flop F'I by a clock pulse signal Op.

At the end of the first group, signal Bc stored is entered into nip-ilop F2 by signal Gp `on channel (Bn-k3). As the second group vof signals Ia'c are being read by reading heads 602cv., reading heads 604 read the corresponding signals of the first group, the signals produced by reading heads EN being then appli'edto gating means 300. Ii signal Bc produced by lflip-'flop F2, at this time, is 1, gating means 300 produces signals O1 corresponding to the selected rsignal Iak If, however, signal Bc is equal to 0 and signal Bc is equal to l, then, at the end of the iirst group, a Asignal Gp is applied to the counter in delay control means 60D, changing its delay ycontrol representation from De1.De2 D' vto De1.De2 DeJ.

Each time signal lBc is equal to 1, gating means 330 produces signals O17, corresponding to the selectec 1 groups of signals lak; and each time signal Bc is equal to l, the delay control counter counts down one, changing its delay c ontrol representation. After (2J-l) signals Bc have `occurred, the delay contlol counter produces a control represen-tation De1.De2 DeJ, indicating that all delay sections are bypassed or that the only delay between the reading of signals Ia.c and the recording of signals O2k is a delay of (GH-S) providei by delay means 4'00. The next time signal Bc is equal to 1, then the delay control representation is changed from 1.751.552 '1761 tonelli@ nel, indicating that the full capacity yof the variable delay means is to Ahe utilized. In effect, this requires that the drum vslip an entire revolution, no output signals Oz* being recorded during this time. It is necessary during this slipping period to prevent reading-writing heads 602 from Writing 0"5" on the drum. For this purpose a biasing nip-flop is included in the writing circuits for heads `6Ii2 and is turned on each time the delay |control coulterhanges fro n '1 a stable state yrepresenting De1.De2 DeJ to a stable state representing Delc2 Del. When the biasing nip-flop is turned on, it is elective to prevent any Writing operation through reading- Writing heads 602. 'The biasing nip-flop circuit is not shown since such circuits are well-known to those skilled in the art.

While the drum circuits shown in Fig. 6 are designed to handle only one sorting problem, it is apparent that it may be duplicated as many times as the drum channel capacity will permit. Thus, yit may be possible to handle 20 sorting operations simultaneously, the results from the individual sortingr operations being collated to provide the desired sequence of information groups.

Circuits for Writing signals onto the magnetic drum and for reading signals from the drum are not shown, since such circuits are Well-known in the art. For example, suitable reading 'and Writing circuits are shown in three patents: U. S. Patent No. 2,540,654, .entitled Data Storage System," 'by A. A. Cohen et al., issued February i6, 1951; U. S. Patent No. 2,609,143, entitled tion, by G. Stibitz, issued September 2, 1952;

and U; S. Patent No. 2,614,169, entitled Storage and Relay Means," by A. Cohen, issued October 14, 1952.

Circuits which may be utilized for starting the sorting operation are not shown, since such cil'- cuits are Well-known in the art. In one type of starting circuit known in the art an operate flipop and a start flip-nop are utilized. The operate flip-flop is turned on when the operator pushes an operating button. As soon as the operate flip-flop is turned on, signal St (recorded on channel (3n-|4) of drum 600) is effective to turn the start flip-flop on, which in turn is eftive to turn the operate flip-flop off. Signals S and S produced by the start flip-flop, then, are utilized to control the operation of selecting vmeans |00, gating mean', 30|), delay control means 00, and sequence control means 10U. Signal S may be utilized to preset the counters and flip-flops prior to operation and signal S to prevent the recording of signals until the operation begins, as signalled by: Szl.

It is apparent from the foregoing description that the present invention provides a novel, serial sorting system for selectively sorting randomly-recorded information groups and recording said groups into a predetermined, evenlyspaced sequence. A high-speed, magnetic drum embodiment of the present invention has been described in detail, although it is understood that the invention is not so limited.

While only two sorting programs have been considered in detail (sorting according to one and two binary digits at a time) and only one type of 'coding (binary) it should be apparent to one skilled in the art that other sorting programs may be utilized as well as other codes without departing from the spirit of the invention.

Suitable structure for each of the means utilized in embodiments of the present invention has been illustrated or incorporated by reference to prior art disclosure. It should be apparent, however, that many substitutions may be made without causing substantial change in the embodiments shown.

What is claimed is:

1. A system for selectively sorting randomlyrecorded information groups and re-recording said groups into a predetermined, evenly-spaced sequence; each of said information groups being represented by a set ofvelectrical signals, includingcode identification signals, said system comprising: selecting means responsive to said code identification signals for producing a binary signal when Van information group is to be selected, and for producing a complementary binary signal when an information group is not to be selected; gating-means responsive to said binary signals and to said sets of electrical signals for producing randomly-spaced sets of output signals corresponding to the selected sets of electrical signals, respectively; variable delay means connected to said gating means for receiving randomly-spacedsets of output signals; and delay control means responsive to said complementary binary signal for applying a ldelay control signal to said'variable delay means to Vary the delayof each of said randomly-spaced sets of output signals to produce corresponding evenly-spaced sets of output signals.

2. A serial sorting system for re-recording randomly-recorded information groups, reprevvsented by sets o1' electrical signals, including code "by passing the information groups through the sorting system a number of times until all groups have been selected; said system comprising: selecting means responsive to said code identication signals for producing complementary binary control signals Bc and Bc corresponding to each information signal group to control its selection or nonselection; gating means responsive to signals Bc and to said sets of electrical signals for producing randomly-spaced sets of output signals O1, corresponding to said selected groups, respecti vely; delay control means responsive to signals vBc for producing delay control signals De; and variable delay means responsive to signals De for delaying signal sets O1 to compensate for spaces corresponding to non-selected sets of electrical signals and for producing evenlyspaced sets of voutput signals Oz.

3. A system for sorting randomly-recorded information groups into a sequence, each of said information groups including data represented by a rst set of electrical signals and 1st, and Nth identification code characters, each including 1st, and Nth binary digits, represented by complementary l iinary digit signals Bdl, Bdl, and Bd", Bd", respectively, said sorting being performed by reading and recording said information groups into 1st, and Nth sequences, successively, according to the binary digits of said lst, andrNth code characters, respectively, said system comprising: selecting matrix means responsive to said binary digit signals for producing binary signals `Bc when said information groups are to be accepted, read, and recorded, and producing complementary binary signals Bc when said information groups are not to be accepted; gating means responsive to said binary signals and to said electrical signals for producing randomly-spaced sets of output signals O1, corresponding to the accepted sets of electrical signals; variable delay means responsive to a delay control signal De for 'delaying each of said signals O1 for a predetermined time interval; and delay control means @ponsive to said complementary binary signals Bc for producing delay control signals De, said variable delay means being responsive to each of said signals De to vary said predetermined time interval as a function ofthe nonacceptance of said information groups.

4. 'I'he system defined in claim 3 Ywherein each of said sequences is formed by producing n subsequences, considering one of said n binary digits ata' time, .said sub-sequences being formed by passing the information groups through the system 2n times; wherein said system further includes sequence control means producing signals Cam indicating theparticular code character to be considered and signals PU) indicating that :ith pass is to be performed, where i is any of the integers l through 2n; and wherein said selecting means is mechanized according to the Boolean algebraic function:

, 5. The system defined in claim 3 wherein each of said sequences is formed by producing n/Z sub-sequences, considering two of said n binary digits at a time, said sub-sequences being formed ,by passing. the. information groups through. the Ysystem. 2n times less.. a. factor. determinediby. the particular binary code utilized; whereinsaid,sys-

tem .furtherincludes .sequence control means producing signals Ca7n indicatingthe particular code character to. be considered and snalsfPM) 1ndicating that. the ith.. pass is to be perfumed,

Qwherea is anyY of the integers 1 through 211;.and wherein said .selecting means is .mechanized according to the Boolean. algebraic function-z signslssaid sorting being. performed.` byl selectivelyV recording the information.y signal groups into a. series of sequences, each-sequence.. being .formed bypassingthe signal-groupsthrou-gh -the system a number of timesuntilall signal groups have. been selected-r. said system comprising:

Asignal source meansfor producing` complemen- -tarysignalszlaand Ia'. for each-character signal seir'during'each odd sequence of said.v series-zA of sequences and -complementary'signals Ib'c and Ibk for' eachA characterl signaal.v setV during each even sequence of saidseries of'sequences, said complementary signals corresponding', respectively, to 4trie-fn.v binary digit signals of 'a character signal seti kibeing anyoi the integersalf through n; sequence control mea'nsrfor producing signals Cw" 'indicating thev'particularfone-foff the N'V code signal' setsfto be considered, .and for producing: signals Pf(j)` indicating the particular passto be performed, m being anyoitheintegers 1i throughN'and :i'being arryrofv thexintegers l tlfiroftsxg-hI 2n; :selectingmeans vforfproducing binary control signals and complementary-- binary control signals Buc" when said ysignal groups .1.

diuring each-even sequence.; gating means-responsive tosignals. Bc. for. producing.. during each sequence,V randomly-spaced groups of cutout sig.-

nais Oi, corresponding. to. said selected signal groups respectively; and variable delay means responsive to signals BE for.'(iilfifi'ing:` signals.: @.1

toprodcceicorresponding :evenly-spaced groupsof output signalsioz', signaiisO constituting Ibl and' ks'and'lsignals yIaklv and Iak of' thelnext succeeding sequencev after each; oddV and even sequence;l respectivelx. 7. The sorting system dened in claim 6; which also includes a magnetic, drum havingn channels for, receiving said.randomlyrecorded information, signal groups. and for receiving signals O2 during said' even sequences; and n channels for, receivingcsignals Oz during saideodd sequences.A

' 8i- The sortingv system defined in claim 7 wherein said magnetic drum includesl a-rstadditional channel forv producing-Si`gna:1sCp,- one; for each digit'ofachannelasecond additional channel for Producing signal group-end-indicating andi a thirdadditionalchannel co- 20 operating with. saidsequence control meansto produce signals Ca'".

9. The sorting system dened in claim. 8, wherein sorting is performed according tor one binary digit signal' at a time and wherein said selecting means includes first and second flipflops Fl and F2 having 'input circuits IFI, DFI and IF2, GFZ, and producing complementary signals F1; F1 and F2, F2 respectively; said selecting means being mechanized according to the Boolean algebraic functions:

0F2=F1-Gfp 10. The sorting systeml defined' in claim. 9, wherein said sequenccontrolmeans also.. pro.- duces signals Ps and-"Ps dened by the Boolean algebraic functions:

Ps=P'(l)+P(2)-| P(2'n'-3)'-1-2`(2n-2)` Ps=P(3)+P(4)+ P(2n-1)'-l-P(2'n) wherendsian even integer; and wherein said ygating means. is mechanized` according tofthe Boolean algebraic. function: a

`l1. The. sorting, system defined, in. claim. 6, *whichr includes a magnetiedrurn havingatleast 2n. channels .for receiving.. signalsOh, an addi.- tonal channel for signal group-end indicating signals G23, and. a furthert channel.- for producing signals Cp, one for each dgitinterval of a channel v l2. The sorting system. dened. in claimili, wherein sorting is performedaccording. to two binary digit signals at a., time and wherein. said 'selecting means'includes rst and seco-nd; flipflops FI and FZhaving input circuitslFl, DFI and IF2, 0F2; Vand producing complementary. sig- QnalsillLIl1 and'F?,1F2,.respectively;. said selecting meansbeing mechanized, according to thelB'oolean algebraic functions:`

-1`EI=Cam[P(T) .l-L-l-al-l-Ft2l1l1 13'.' The-sorting system dened' in claimt. 1'2, wherein. said sequenoe control vmeans also produces signals Psy and Ps defined-by the Boolean algebraic functions:

Ps=P l)-i-P(2)-I.P(3)|P(4)' Referencesf Cited in the file: ofthis-patent UNITED STATES"r'kll'l'lllN'IS Number Name Date 2,3.86g743' Mayet. al. Oct. 9, 1945 I2,649,513 Luhn Aug.. 18;Y 1953 

